Microprocessor Report (MPR) Subscribe

Ncore 3.0 Flexes Interface Chops

October 16, 2017

By Loyd Case


ArterisIP is continuing a steady pace of updates to its Ncore intellectual property (IP) for coherent network-on-a-chip (NoC) interconnects, adding Ace, Chi, and CCIX interoperability. Ncore 3.0 also adds optimizations that enable designers to target a 2.0GHz clock frequency in 16nm designs. This latest version, announced at the recent Linley Processor Conference, has been available to a few early customers; wide release is slated for 2Q18.

ArterisIP (formerly called Arteris) delivered the first Ncore NoC IP in 2016, offering coherent-interconnect capability for the first time. It followed in April of this year by adding its Resilience package, which brings optional IP and tools that allow Ncore users to more easily meet ISO 26262 safety requirements (see MPR 4/24/17, “Arteris Ncore 2.0 Simplifies Safety”). Resilience targets autonomous-driving ASICs that combine CPUs, GPUs, and other heterogeneous but coherent cores.

Arm’s Chi is a coherent fabric that often serves in Cortex-based multicore processors. The CCIX standard effectively extends Chi to handle coherent chip-to-chip connections (see MPR 6/6/16, “CCIX: Coherent Interconnect for All”), so ArterisIP enabled it in its latest IP. Ncore 3.0 works with CCIX coherent agents that link to the external CCIX PHY and controllers, converting CCIX protocols to its internal NoC protocols. It maintains coherence throughout the transaction, which can span multiple chips. The CCIX agent communicates with the NoC’s snoop filters to locate the requested data in any coherent master on any chip in the system. This approach allows developers to design application-specific SoCs, such as hardware accelerators, using Ncore 3.0 and connect them coherently to other CCIX-compatible SoCs.

The new IP also enables SoC designers to integrate Ace coherent interfaces. When communicating with noncoherent agents using Amba AXI or Ace-Lite, Ncore’s proxy cache allows those agents to participate in the coherent system. As with the CCIX-agent interface, the Ace agent converts Ace protocols to internal protocols.

The new NoC supports SoC design using a variety of topologies, including trees, rings, and meshes. When designers employ a tree topology, Ncore uses shared data paths to reduce the necessary number of wires; it can also implement crossbar connections to boost throughput. The NoC handles mesh topologies ranging from simple 2D grids to cubes, tori, and other 3D structures.

Ncore 3.0 allows ArterisIP customers to more easily integrate third-party agents created for other interconnect technologies. Since many of these customers design their own secondary processors or hardware accelerators that must coexist with host processors based on other interconnects, the new design makes life much easier.

Events

Linley Fall Processor Conference 2018
Covers processors and IP cores used in embedded, communications, automotive, IoT, and server designs.
October 31 - November 1, 2018
Hyatt Regency, Santa Clara, CA
More Events »

Newsletter

Linley Newsletter
Analysis of new developments in microprocessors and other semiconductor products
Subscribe to our Newsletter »