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Ceva PentaG Adds AI to 5G Baseband

Neural-Network Engine Optimizes for Variable Channel Conditions

March 12, 2018

By Mike Demler


Ceva’s new PentaG DSP comprises a set of configurable processing blocks that allow designers to build digital basebands implementing the recently ratified 3GPP 5G New Radio (5G-NR) specification. This intellectual property (IP) includes the company’s previously released XC-4500 LTE-Advanced DSP and X2 PHY controllers, enabling backward compatibility with previous-generation cellular standards. But it also extends the XC-4500 ISA with 5G-specific instructions and adds hardware accelerators for the new 5G channel-coding formats. Other new PentaG features include a vector multiply-accumulate (MAC) coprocessor and a neural-network engine that delivers 400 billion operations per second (GOPS). The neural engine runs deep-learning algorithms that handle 5G link optimization.

PentaG uses a modular approach, allowing customers to choose the components they need to add 5G capabilities to existing designs. The company licenses it as a complete hardware/software platform; alternatively, customers can license each component separately. Ceva plans to begin licensing PentaG to lead customers in 2Q18 and to begin general licensing in 3Q18.

Focus on 5G

In December, the 3GPP ratified some 5G-NR specifications in the Release 15 standard, but only for the non-standalone (NSA) mode that uses existing LTE infrastructure for core network functions, as Figure 1 shows. In 1Q18, it plans to release the NSA Option 3 Abstract Syntax Notation One (ASN.1) pseudocode, which manufacturers use to convert the specifications to interoperable software. By separating the NSA specifications from standalone (SA) mode, the 3GPP aims to enable the first 5G deployments in 2019, one year earlier than originally planned. It intends to release SA specifications by midyear, enabling 5G systems to implement the new control protocols.

 

Figure 1. The 3GPP’s 5G-NR development schedule. The 5G-NR Release 15 standard for enhanced mobile broadband (EMBB), including both sub-6GHz and millimeter-wave bands, is divided into non-standalone (NSA) and standalone (SA) modes.

The term 5G is actually an umbrella for three different sets of services: enhanced mobile broadband (EMBB), massive machine-type communications (MMTC), and ultra-reliable low-latency communications (URLLC). The 3GPP plans to include MMTC and URLLC in its mid-2019 Release 16 specifications. MMTC increases network capacity for IoT devices, and URLLC will support factory automation, intelligent transportation services, and other applications requiring millisecond latency.

The first 5G deployments will focus exclusively on EMBB, which can theoretically deliver up to 10Gbps peak downlink speeds, rolling off to 100Mbps at cell edges. PentaG addresses that use case, targeting gigabit 5G radios in smartphones as well as embedded devices and fixed-wireless modems. PentaG supports the initial 5G-NR deployments using sub-6GHz and millimeter-wave spectrum, and it’s software upgradable to support future 3GPP releases.

From Base Stations to Terminals

PentaG isn’t Ceva’s first 5G baseband design. Last year, the company rolled out the XC12 DSP for 5G infrastructure, but the software-defined radio (SDR) in that product consumes too much power for smartphones and other terminals (see MPR 4/3/17, “Ceva Telegraphs 5G Intent With XC12”). PentaG uses less power by employing fewer programmable units, shifting more of the processing to dedicated hardware accelerators.

The XC4500 vector DSP is the 4G predecessor to the XC12, but as Figure 2 shows, it serves as the base processor core in PentaG (see MPR 11/4/13, “Ceva Targets Wireless Infrastructure”). Although Ceva originally positioned the XC4500 for LTE-Advanced infrastructure, the design is highly configurable, and two smartphone-chip customers use it in handsets. Designers can optionally include a 32KB instruction cache along with a 16KB, 32KB, or 64KB data cache, or they can omit both. The instruction and data tightly coupled memories (TCMs) are also configurable: 32–512KB for the former and 128–1,024KB for the latter.

 

Figure 2. Ceva 5G baseband DSP. PentaG reuses the XC4500 and X2 cores, but to support 5G-NR, it adds new features including hardware accelerators, a neural-network engine, and a vector coprocessor. In this dual-baseband configuration, one 5G module handles sub-6GHz communications and a second module handles millimeter-wave bands.

To maintain software compatibility for legacy 3G and 4G systems, Ceva left the XC4500 core unchanged from the current production model. Rather than modify the architecture for 5G, it used the Xtend tool it supplies to licensees that wish to add custom instructions. Although the 5G extensions are an add-on to the XC4500, modem designers can take advantage of the new features to enhance 4G performance as well. For example, channel-state-information (CSI) tasks run 10x faster than on the original XC4500 core. The PentaG ISA includes new physical-downlink-control-channel (PDCCH) extensions, which run 4x faster thanks to the new instructions and vector unit.

A Building Block That Floats

Along with the ISA additions, PentaG meets the greater 5G performance requirements by augmenting the XC4500 with a programmable 64-MAC vector coprocessor. The vector unit implements a block-floating-point (BFP) architecture, which uses fixed-point hardware to emulate 16x16-bit floating-point calculations.

As Figure 3 shows, BFP algorithms apply a single exponent to a data block. To use this technique, the processor must track the magnitudes of samples in a block of data, such as the input to an FFT, and normalize the mantissas to fit the range of the common exponent. Although the dynamic range is the same as with fixed-point arithmetic, BFP increases precision. It’s also faster than standard floating point, and it eliminates the area and power required to store and calculate exponents for each input sample. The XC4500 integrates 64 floating-point MACs as well, but they don’t use BFP. To maximize speed using that vector DSP, designers can employ non-IEEE-compliant floating-point MACs or select fully IEEE-754-compliant ones.

 

Figure 3. Block-floating-point calculations. The BFP method saves area and power by emulating the same dynamic range using fixed-point hardware. The processor scales the mantissas to share a single exponent, which changes in accordance with the data block’s magnitude.

The vector coprocessor handles generic matrix processing, but it also comes with special-purpose instructions for tasks such as physical-downlink-shared-channel (PDSCH) estimation, which requires calculations over frequency and time. It performs the more numerous matrix multiplications that 5G requires owing to its 5x greater channel bandwidth (up to 100MHz) relative to LTE and its use of massive-MIMO antenna arrays. Release 15 allows transmit-antenna arrays comprising up to 64 elements.

The 5G-NR radio employs different encode/decode techniques than an LTE radio. Whereas LTE uses turbo and Viterbi encoders, the 3GPP adopted low-density parity check (LDPC) for EMBB data channels and polar codes for the control channel. LDPC is a proven coding technique that serves in IEEE 802.11n and later Wi-Fi standards (see MPR 2/12/12, “Wireless Wants to Wallop Wires”). Because polar codes offer advantages over LPDC and turbo for small workloads, the 3GPP working groups are considering them for both data and control channels in 5G MMTC and URLLC services, which employ smaller messages than EMBB. PentaG efficiently handles these channel-coding tasks with LPDC and polar encode/decode hardware accelerators.

To address 5G’s complex carrier-aggregation and MIMO needs, PentaG integrates two X2 PHY controllers connected through AXI ports, but customers can add more if necessary (see MPR 8/1/16, “Ceva X2 Controls Multiple PHYs”). They can configure the X2 with up to 64KB of data cache and up to 128KB of instruction cache. The instruction TCM can be as much as 256KB, and the data TCM can be as much as 512KB.The X2 cluster and XC4500 baseband module share the L2 cache, which is configurable from 2KB to 2,048KB. For 5G modems that support both sub-6GHz and millimeter-wave radios, designers must integrate two complete baseband modules that run in parallel. A single dual-X2 cluster can control both modules.

Adding Intelligence

One of the toughest processing challenges for 5G-NR modems is running the CSI analysis by which a terminal optimizes its communications with the base station. Delivering EMBB’s gigabit speeds requires dynamic link adaptation, which optimizes transmissions according to channel noise, signal strength, and other conditions. The base station transmits pilot signals to devices in its cell area, but conditions at the terminal will vary, especially for mobile devices. LTE-Advanced also uses CSI, but the 5G-NR processing requirements are 5x greater, according to Ceva’s estimates.

To optimize reception, a 5G terminal analyzes the signals it receives from the base station’s antenna array and sends back data describing the quality of each one. The base-station radio then tunes the channel it uses to communicate with the terminal, choosing the optimum settings for beam forming, channel frequencies, MIMO, QAM, and other parameters. The PentaG neural engine performs this channel-state analysis automatically. It can run the analyses either separately on a set of small neural networks or all together on a single network. The company withheld details, but we expect it based the PentaG neural engine on its XM4 computer-vision engine (see MPR 4/27/15, “Ceva Sharpens Computer Vision”). This phase-one design handles Release 15 requirements, but Ceva believes it’s scalable for future Release 16 specifications.

To train PentaG’s neural networks, modem designers employ a simulator that models the range of expected channel conditions and system variables. Ceva provides the training software, but designers must build the models for the inference engine, taking into account the hardware in each modem. Although LTE modems typically run this channel model in software on the modem CPU, that technique is too slow for the more complex 5G tasks. Another LTE technique involves using a large lookup table to store each modem parameter, but 5G’s more complex nonlinear channel behavior makes achieving adequate resolution difficult with such an approach.

Accelerating 5G Development

Ceva has at least two high-volume customers for its LTE baseband IP, yielding total shipments in excess of 200 million units per year. Samsung has relied on Ceva ever since its first LTE chip appeared in 2010. Spreadtrum also uses Ceva’s LTE designs in many of its smartphone processors. As a result of this ongoing customer demand, Ceva has consistently invested in upgrading its baseband designs to keep pace with the latest 3GPP standards, which now include 5G-NR.

In contrast, other cellular IP suppliers have let their products lapse. Cadence hasn’t upgraded its LTE architecture since introducing the BBE64 seven years ago (see MPR 3/21/11, “Tensilica DSP Targets LTE Advanced”), although Intel continues to use a heavily customized Tensilica core in its LTE modems. Asocs briefly challenged Ceva for base-station designs (see MPR 6/25/12, “Asocs Rocks the Baseband-IP Market”), but it has withdrawn from the IP-licensing market. Although Arm’s Cortex-R8 CPU competes with the X2 for 5G PHY control, that IP vendor lacks the DSP components to build a complete baseband design (see MPR 3/14/16, “ARM Revs Up Cortex-R8 for 5G”).

Ceva’s primary competition is thus the internal DSP designs at companies such as Huawei, Intel, MediaTek, and Qualcomm. Ceva believes PentaG’s modular approach opens new opportunities at such companies. Its neural-network link-optimization engine, for example, solves a critical problem for 5G modems. Ceva is willing to separately license that engine, which other companies could combine with their proprietary DSP designs.

With PentaG, Ceva is accelerating 5G development by offering a complete hardware/software solution that is well suited to companies wishing to enter the 5G market, either for smartphones or for emerging segments such as cellular PCs or fixed-wireless broadband. The platform’s reuse of LTE-Advanced components gives existing licensees an easy upgrade path to 5G. Ceva supports PentaG designs with simulation tools, 5G-NR DSP libraries, and a real-time operating system. The software kit includes tools for training PentaG’s neural-network engine. Designers can also use the company’s FPGA development board and drivers to prototype their modem hardware and software before receiving working silicon.

There’s been no shortage of hype surrounding 5G rollouts, as few operators control the necessary bandwidth to deliver multigigabit speeds using LTE (see MPR 3/5/18, “5G Reaches Peak Hype”). To address this issue, regulators are opening up new spectrum in the unlicensed 3.5GHz band (see MPR 2/19/18, “Cellular Moves Into Unlicensed Bands”). In the U.S., network operators have begun testing 5G using 28GHz millimeter-wave radios, which will mostly serve dense urban areas. PentaG offers modem designers the tools they need to use all these bands in high-speed 5G-NR terminals, and its software configurability allows addition of the new features coming with future 3GPP releases.

Price and Availability

PentaG will be available for licensing to Ceva’s lead customers in 2Q18. The company plans general availability in 3Q18. It declined to reveal pricing. For more information on PentaG, access www.ceva-dsp.com/product/ceva-pentag.

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